The common tendency of microelectronic circuit is to integrate more functions on the chip in order to increase the widely applications of electric circuit, reduce the size and power consumption of system, and lower the price of devices. Although the bipolar transistor and bipolar process technology do not suit all applications, they are some key foundations for other extended process technology, like BiCMOS and BiCDMOS, for a long time.
Generally there is no good PNP transistor in most bipolar processes, because this process generally is designed to make the best performance of vertical NPN transistor. Although the vertical PNP may be added into the manufacturing process, it will increase the process complexity, number of mask, and cost.
The lateral PNP (LPNP) transistor is the P-type device mainly used, because the requests about high frequency performance, current driving capability, packing density and so on for LPNP transistor are lower than vertical NPN transistor.
Generally, the LPNP transistor is made by two nearby P-type areas which diffused into epi layer with one P-type collector surrounding another P-type emitter. In the most processes, the base is formed by N-type epi layer and N+ contact area. Collector and emitter are separated by the field oxide.
Because the bipolar process is generally aimed to optimize the performance of NPN transistor, the lateral PNP transistor is made by the layers that also used by NPN transistor. FIG. 1 is the enlarged cross section of general LPNP transistor. Referring to FIG. 1, a buried N layer 11 is formed on a P-type doping substrate 10. The N-type epi layer 12 is grown on buried N layer 11 and the N-type field implant layer 120 is formed on epi layer 12. Then a P+ isolation area 121 is diffused from the surface of field implant layer 120 to P-type buried area 111 on substrate 10. The buried layer 11 is surrounded by isolation area 121 and P-type buried area 111. The epi layer 12 that is surrounded by isolation area 121 has numerous diffusion areas, such as N-type slot area 134 (generally is N+ sinker of NPN or N-well of CMOS) which diffuses from the surface of epi oxide layer 14 to the edge of buried layer 11, P+-type emitter area 132 and P+-type collector area 131 which surround and separated with emitter area 132 (generally is P-base of NPN or P+ of CMOS). The N+-type area 135 (generally is N+-emitter of NPN or N+ of CMOS) which formed in slot area 134 is used as base to provide current for epi layer 12 through slot area 134 and buried layer 11. The contact holes of N+-type area 135 and collector areas 131 and emitter area 132 are formed on oxide layers 14 which on the epi layer 12 with field effect implant layer 120. Finally, the base electrode metal 143 and collector electrode metal 141 and emitter electrode metal 142 are formed in contact holes and connected with N+-type area 135 and collector areas 131 and emitter area 132, respectively.
Although the current gain and the driving capability of LPNP can be enhanced by heavier doping emitter area 132 and collector 131 and deeper P+ junction in the previous art, the collector-base breakdown voltage (BVceo) and Early voltage (VA) of LPNP transistor were decreased. Owing to the limitations of LPNP performance, either big area LPNP or complicated circuit design will be needed to satisfy the request of the product.
Further, the weak point of previous LPNP is mainly caused by its base area doping is same as lightly doped NPN collector area doping. In order to reach the request of collector-base breakdown voltage (BVceo) and Early voltage (VA), the distance between emitter 132 and collector 131 must be enough, that means a wider base width is needed, but actually therefore has sacrificed the current gain. Although the current gain can be enhanced by heavier doped emitter and collector area and deeper P+ junction due to the emitter emission efficiency increased at present, its effects is not obvious since the base width is the primary factor to decide the current gain (Hfe).